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40 lines
751 B
40 lines
751 B
library ieee ;
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use ieee.std_logic_1164.all;
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-- Async reset synchronizer circuit inspired from
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-- Chris Cummings SNUG 2002 paper
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-- Synchronous Resets? Asynchronous Resets?
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-- I am so confused!
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-- How will I ever know which to use?
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entity reset_sync is
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generic (
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POLARITY : std_logic := '0'
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);
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port (
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clk_i : in std_logic;
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rst_i : in std_logic;
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rst_o : out std_logic
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);
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end entity;
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architecture sim of reset_sync is
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signal s_rst_d : std_logic_vector(1 downto 0);
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begin
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process (clk_i, rst_i) is
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begin
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if (rst_i = POLARITY) then
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s_rst_d <= (others => POLARITY);
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elsif (rising_edge(clk_i)) then
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s_rst_d <= s_rst_d(0) & not POLARITY;
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end if;
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end process;
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rst_o <= s_rst_d(1);
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end architecture;
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