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135 lines
3.4 KiB
135 lines
3.4 KiB
-- UART register
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-- Register file with 8 registers storing values of one byte each.
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--
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-- The first received byte on the axis in port contains command & address:
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--
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-- 7 reserved
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-- 6:4 register address
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-- 3:0 command
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-- 0x0 read
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-- 0x1 write
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--
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-- In case of a write command, the payload has to follow
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-- with the next byte.
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--
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-- In case of a read command, the value of the addressed
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-- register is returned on the axis out port.
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--
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-- Register at address 0 is special. It contains the version
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-- and is read-only. Writes to that register are ignored.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity uart_ctrl is
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port (
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-- globals
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rst_n_i : in std_logic;
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clk_i : in std_logic;
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-- axis in
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tdata_i : in std_logic_vector(7 downto 0);
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tvalid_i : in std_logic;
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tready_o : out std_logic;
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-- axis out
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tdata_o : out std_logic_vector(7 downto 0);
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tvalid_o : out std_logic;
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tready_i : in std_logic
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);
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end entity uart_ctrl;
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architecture rtl of uart_ctrl is
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type t_state is (IDLE, GET_CMD, RECV_DATA, SEND_DATA);
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signal s_state : t_state;
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subtype t_reg is std_logic_vector(7 downto 0);
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type t_reg_file is array (1 to 7) of t_reg;
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signal s_reg_file : t_reg_file;
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constant c_version : t_reg := x"01";
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signal s_reg_addr : natural range 0 to 7;
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signal s_reg_data : t_reg;
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subtype t_cmd is std_ulogic_vector(3 downto 0);
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constant c_read : t_cmd := x"0";
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constant c_write : t_cmd := x"1";
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alias a_tdata_cmd is tdata_i(3 downto 0);
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alias a_tdata_addr is tdata_i(6 downto 4);
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begin
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-- Register memory, omitted reset of memory during synthesis
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-- for better RAM detection
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process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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-- synthesis translate_off
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s_reg_file <= (others => (others => '0'));
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-- synthesis translate_on
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s_reg_data <= (others => '0');
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elsif (rising_edge(clk_i)) then
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-- Write
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if (s_state = RECV_DATA and tvalid_i = '1') then
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-- Ignore writes to version register
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if (s_reg_addr /= 0) then
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s_reg_file(s_reg_addr) <= tdata_i;
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end if;
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end if;
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-- Always read, regardless of write or read command
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if (s_state = GET_CMD) then
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if (s_reg_addr /= 0) then
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s_reg_data <= s_reg_file(s_reg_addr);
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end if;
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end if;
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end if;
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end process;
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-- Control state machine
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process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_state <= IDLE;
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s_reg_addr <= 0;
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elsif (rising_edge(clk_i)) then
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case s_state is
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when IDLE =>
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if (tvalid_i) then
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s_state <= GET_CMD;
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s_reg_addr <= to_integer(unsigned(a_tdata_addr));
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end if;
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when GET_CMD =>
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if (a_tdata_cmd = c_read) then
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s_state <= SEND_DATA;
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elsif (a_tdata_cmd = c_write) then
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s_state <= RECV_DATA;
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else
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s_state <= IDLE;
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end if;
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when RECV_DATA =>
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if (tvalid_i) then
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s_state <= IDLE;
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end if;
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when SEND_DATA =>
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if (tready_i) then
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s_state <= IDLE;
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end if;
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when others =>
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null;
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end case;
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end if;
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end process;
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tready_o <= '1' when s_state = GET_CMD or s_state = RECV_DATA else '0';
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tdata_o <= c_version when s_reg_addr = 0 else s_reg_data;
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tvalid_o <= '1' when s_state = SEND_DATA else '0';
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end architecture;
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