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gatemate_experiments/uart_aes
T. Meissner bb98b0e5f5 Add comments with some hints to yosys & p_r options and their effects 2 years ago
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rtl Add comments with some hints to yosys & p_r options and their effects 2 years ago
sim Add uart_aes design, simulation & fpga-flow 2 years ago
syn Add comments with some hints to yosys & p_r options and their effects 2 years ago