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gatemate_experiments
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gatemate_experiments/uart_loop/rtl
T. Meissner 6b1b376932 Use speed instead of moderate FPGA speed grade 2 years ago
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uart_loop.vhd Use speed instead of moderate FPGA speed grade 2 years ago
uart_rx.vhd Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
uart_tx.vhd Add uart_loop design to test gatemate fifo & ram primitives 2 years ago