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gatemate_experiments
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gatemate_experiments/uart_reg/rtl
T. Meissner 6b1b376932 Use speed instead of moderate FPGA speed grade 2 years ago
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uart_ctrl.vhd Update uart_reg to full reg file implementation 2 years ago
uart_reg.vhd Use speed instead of moderate FPGA speed grade 2 years ago
uart_rx.vhd Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
uart_tx.vhd Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago