Library of reusable VHDL components
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. entity WishBoneMasterE is
  5. generic (
  6. G_ADR_WIDTH : positive := 8; --* address bus width
  7. G_DATA_WIDTH : positive := 8 --* data bus width
  8. );
  9. port (
  10. --+ wishbone system if
  11. WbRst_i : in std_logic;
  12. WbClk_i : in std_logic;
  13. --+ wishbone outputs
  14. WbCyc_o : out std_logic;
  15. WbStb_o : out std_logic;
  16. WbWe_o : out std_logic;
  17. WbAdr_o : out std_logic_vector(G_ADR_WIDTH-1 downto 0);
  18. WbDat_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  19. --+ wishbone inputs
  20. WbDat_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
  21. WbAck_i : in std_logic;
  22. WbErr_i : in std_logic;
  23. --+ local register if
  24. LocalWen_i : in std_logic;
  25. LocalRen_i : in std_logic;
  26. LocalAdress_i : in std_logic_vector(G_ADR_WIDTH-1 downto 0);
  27. LocalData_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
  28. LocalData_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
  29. LocalAck_o : out std_logic;
  30. LocalError_o : out std_logic
  31. );
  32. end entity WishBoneMasterE;
  33. architecture rtl of WishBoneMasterE is
  34. type t_wb_master_fsm is (IDLE, ADDRESS, DATA);
  35. signal s_wb_master_fsm : t_wb_master_fsm;
  36. signal s_wb_wen : std_logic;
  37. begin
  38. --+ Wishbone master control state machine
  39. WbMasterStatesP : process (WbClk_i) is
  40. begin
  41. if (rising_edge(WbClk_i)) then
  42. if (WbRst_i = '1') then
  43. s_wb_master_fsm <= IDLE;
  44. else
  45. WbReadC : case s_wb_master_fsm is
  46. when IDLE =>
  47. if ((LocalWen_i xor LocalRen_i) = '1') then
  48. s_wb_master_fsm <= ADDRESS;
  49. end if;
  50. when ADDRESS =>
  51. if (WbAck_i = '1' or WbErr_i = '1') then
  52. s_wb_master_fsm <= IDLE;
  53. else
  54. s_wb_master_fsm <= DATA;
  55. end if;
  56. when DATA =>
  57. if (WbErr_i = '1' or WbAck_i = '1') then
  58. s_wb_master_fsm <= IDLE;
  59. end if;
  60. when others =>
  61. s_wb_master_fsm <= IDLE;
  62. end case;
  63. end if;
  64. end if;
  65. end process WbMasterStatesP;
  66. --+ combinatoral local register if outputs
  67. LocalData_o <= WbDat_i when s_wb_master_fsm = DATA else (others => '0');
  68. LocalError_o <= WbErr_i when s_wb_master_fsm /= IDLE else '0';
  69. LocalAck_o <= WbAck_i when (s_wb_master_fsm = ADDRESS or s_wb_master_fsm = DATA) and WbErr_i = '0' else '0';
  70. --+ combinatoral wishbone if outputs
  71. WbStb_o <= '1' when s_wb_master_fsm /= IDLE else '0';
  72. WbCyc_o <= '1' when s_wb_master_fsm /= IDLE else '0';
  73. WbWe_o <= s_wb_wen when s_wb_master_fsm /= IDLE else '0';
  74. --+ registered wishbone if outputs
  75. OutRegsP : process (WbClk_i) is
  76. begin
  77. if(rising_edge(WbClk_i)) then
  78. if(WbRst_i = '1') then
  79. WbAdr_o <= (others => '0');
  80. WbDat_o <= (others => '0');
  81. s_wb_wen <= '0';
  82. else
  83. if (s_wb_master_fsm = IDLE) then
  84. if ((LocalWen_i xor LocalRen_i) = '1') then
  85. WbAdr_o <= LocalAdress_i;
  86. s_wb_wen <= LocalWen_i;
  87. end if;
  88. if (LocalWen_i = '1') then
  89. WbDat_o <= LocalData_i;
  90. end if;
  91. end if;
  92. end if;
  93. end if;
  94. end process OutRegsP;
  95. -- psl default clock is rising_edge(WbClk_i);
  96. -- PSL assert directives
  97. -- psl RESET : assert always
  98. -- WbRst_i ->
  99. -- WbCyc_o = '0' and WbStb_o = '0' and WbWe_o = '0' and
  100. -- to_integer(unsigned(WbAdr_o)) = 0 and to_integer(unsigned(WbDat_o)) = 0 and
  101. -- LocalAck_o = '0' and LocalError_o = '0' and to_integer(unsigned(LocalData_o)) = 0
  102. -- report "WB master: Reset error";
  103. --
  104. -- psl WB_WRITE : assert always
  105. -- ((not(WbCyc_o) and not(WbStb_o) and LocalWen_i and not (LocalRen_i)) ->
  106. -- next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '1')) abort WbRst_i
  107. -- report "WB master: Write error";
  108. --
  109. -- psl WB_READ : assert always
  110. -- ((not(WbCyc_o) and not(WbStb_o) and LocalRen_i and not(LocalWen_i)) |->
  111. -- next (WbCyc_o = '1' and WbStb_o = '1' and WbWe_o = '0')) abort WbRst_i
  112. -- report "WB master: Read error";
  113. -- PSL cover directives
  114. -- psl COVER_LOCAL_WRITE : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
  115. -- LocalRen_i = '0' and WbRst_i = '0'}
  116. -- report "WB master: Local write";
  117. --
  118. -- psl COVER_LOCAL_READ : cover {s_wb_master_fsm = IDLE and LocalRen_i = '1' and
  119. -- LocalWen_i = '0' and WbRst_i = '0'}
  120. -- report "WB master: Local read";
  121. --
  122. -- psl COVER_LOCAL_WRITE_READ : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
  123. -- LocalRen_i = '1' and WbRst_i = '0'}
  124. -- report "WB master: Local write & read";
  125. end architecture rtl;