Library of reusable VHDL components
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  1. # libvhdl
  2. A LGPLv3 licensed library of reusable components for VHDL designs and testbenches
  3. ##sim
  4. (Non) synthesible components for testbenches
  5. ##### AssertP
  6. Package with various assertion procedures.
  7. * `assert_true(x[, str, level])` checks if boolean x = false
  8. * `assert_false(x[, str, level])` checks if boolean x = false
  9. * `assert_equal(x, y[, str, level])` checks if x = y
  10. * `assert_unequal(x, y[, str, level])` checks if x /= y
  11. All of the assert_* procedures have following optional parameters:
  12. * `str` print string str to console instead implemented one
  13. * `level` severity level (note, warning, error, failure)
  14. ##### SimP
  15. Package with various components general useful for simulation
  16. * `wait_cycles(x, n)` waits for n rising edges on std_logic signal x
  17. * `spi_master()` configurable master for SPI protocol, supports all cpol/cpha modes
  18. * `spi_slave()` configurable slave for SPI protocol, supports all cpol/cpha modes
  19. ##### QueueP
  20. Package with various implementations of queue types:
  21. * `t_simple_queue` simple array based FIFO queue
  22. * `t_list_queue` linked list FIFO queue using access types
  23. ## syn
  24. Synthesizable components for implementing in FPGA
  25. ##### SpiMasterE
  26. Configurable SPI master with support modes 0-3 and simple VAI local backend.
  27. ##### SpiSlaveE
  28. Configurable SPI slave with support modes 0-3 and simple VAI local backend.
  29. ##### WishBoneMasterE
  30. Simple WishBone bus master with support of classic single write & read
  31. ##### WishBoneSlaveE
  32. Simple WishBone bus slave with support of classic single write & read and register backend
  33. ##test
  34. Unit tests for each component
  35. ##### QueueT
  36. Unit tests for components of QueueP package
  37. ##### SimT
  38. Unit tests for components of SimP package
  39. ##### SpiT
  40. Unit tests for SpiMasterE and SpiSlaveE components
  41. ##### WishBoneT
  42. Unit tests for WishBoneMasterE and WishBoneSlaveE components
  43. ## Dependencies
  44. To run the tests, you have to install GHDL. You can get it from
  45. [http://sourceforge.net/projects/ghdl-updates/](http://sourceforge.net/projects/ghdl-updates/).
  46. Furthermore, you need the VHDL-2008 proposed packages because libvhdl uses various VHDL-2008 features. To get the needed files, you can use the get_vhdl_2008.sh script which downloads the files into the vhdl_2008 folder and patches the env_c.vhdl file to get in compiled with GHDL.
  47. If you another simulator with full VHDL-2008 support, you don't need these packages. Instead you have to outcomment
  48. the references to these packages from the source files.
  49. libvhdl also uses the OSVVM library to generate random data for the unit tests. We use version OSVVM version 2.1
  50. because of restrictions of the current GHDL release. You can find it under the osvvm_2.1 folder in the test/
  51. directory. If you use another simulator with full OSVVM support, you can download newer versions of the library
  52. from [http://osvvm.org](http://osvvm.org).
  53. Another useful tool is GTKWave, install it if you want to use the waveform files generated by some of the tests.
  54. ## Building
  55. Type `make` to do all tests. You should see the successfully running tests like this:
  56. ```
  57. $ make
  58. ghdl -a --std=02 ../sim/QueueP.vhd QueueT.vhd
  59. ghdl -e --std=02 QueueT
  60. ghdl -r --std=02 QueueT
  61. QueueT.vhd:52:5:@0ms:(report note): INFO: t_simple_queue test finished successfully
  62. QueueT.vhd:87:5:@0ms:(report note): INFO: t_list_queue test finished successfully
  63. ```