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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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library libvhdl; |
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use libvhdl.StringP.all; |
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use libvhdl.AssertP.all; |
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entity StringT is |
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end entity StringT; |
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architecture sim of StringT is |
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begin |
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StringTestP : process is |
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variable v_data : std_logic_vector(31 downto 0) := x"DEADBEEF"; |
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variable v_data_reverse : std_logic_vector(0 to 31) := x"DEADBEEF"; |
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begin |
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assert_equal(to_string(v_data(0)), "1"); |
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assert_equal(to_string(v_data), "11011110101011011011111011101111"); |
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assert_equal(to_string(v_data_reverse), "11011110101011011011111011101111"); |
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report "INFO: StringP tests finished successfully"; |
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wait; |
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end process StringTestP; |
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end architecture sim; |
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