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@ -104,7 +104,6 @@ begin |
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v_bit_counter := C_BIT_COUNTER_START; |
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v_sclk_counter := G_SCLK_DIVIDER-1; |
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s_transfer_valid <= false; |
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s_ste <= '1'; |
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s_sclk <= std_logic'val(G_SPI_CPOL+2); |
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s_mosi <= '1'; |
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s_spi_state <= IDLE; |
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@ -112,15 +111,13 @@ begin |
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case s_spi_state is |
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when IDLE => |
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s_ste <= '1'; |
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s_sclk <= std_logic'val(G_SPI_CPOL+2); |
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s_mosi <= '0'; |
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s_mosi <= '1'; |
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s_recv_register <= (others => '0'); |
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v_bit_counter := C_BIT_COUNTER_START; |
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v_sclk_counter := G_SCLK_DIVIDER/2-1; |
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s_transfer_valid <= false; |
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if(DataValid_i = '1' and s_data_accept = '1') then |
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s_ste <= '0'; |
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s_spi_state <= WRITE; |
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end if; |
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@ -182,7 +179,6 @@ begin |
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when SET_STE => |
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s_transfer_valid <= false; |
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s_ste <= '1'; |
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if (v_sclk_counter = 0) then |
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s_spi_state <= IDLE; |
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else |
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@ -218,12 +214,15 @@ begin |
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end process RecvRegisterP; |
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--+ internal signals |
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s_ste <= '1' when s_spi_state = IDLE or s_spi_state = SET_STE else '0'; |
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--+ Output port connections |
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DataValid_o <= s_data_valid; |
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DataAccept_o <= s_data_accept; |
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SpiSte_o <= s_ste; |
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SpiSclk_o <= s_sclk; |
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SpiMosi_o <= s_mosi; |
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SpiSte_o <= s_ste; |
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SpiSclk_o <= s_sclk; |
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SpiMosi_o <= s_mosi when s_ste = '0' else '1'; |
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assert G_SCLK_DIVIDER rem 2 = 0 |
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