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@ -45,8 +45,8 @@ Synthesizable components for implementing in FPGA |
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Configurable SPI slave with support modes 0-3 and simple VAI local backend. |
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Implementation results: |
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* 49 logic elements utilization, 397 MHz clock frequency on Microsemi SmartFusion2, speed grade STD |
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* 24 slices utilization, 649 MHz clock frequency on Xilinx Kintex7, speed grade -3 |
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* Microsemi SmartFusion2 (speed grade std): 49 logic elements, 397 MHz on |
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* Xilinx Kintex7 (speed grade -3): 24 slices, 649 MHz on |
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##test |
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