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Use generics to set vector lenghts instead of unconstrained vectors

master
T. Meissner 5 years ago
parent
commit
ea5a71fdff
2 changed files with 41 additions and 30 deletions
  1. +28
    -21
      syn/WishBoneMasterE.vhd
  2. +13
    -9
      syn/WishBoneSlaveE.vhd

+ 28
- 21
syn/WishBoneMasterE.vhd View File

@ -4,6 +4,11 @@ library ieee;
entity WishBoneMasterE is entity WishBoneMasterE is
generic (
Coverage : boolean := false;
AddressWidth : natural := 8;
DataWidth : natural := 8
);
port ( port (
--+ wishbone system if --+ wishbone system if
WbRst_i : in std_logic; WbRst_i : in std_logic;
@ -12,18 +17,18 @@ entity WishBoneMasterE is
WbCyc_o : out std_logic; WbCyc_o : out std_logic;
WbStb_o : out std_logic; WbStb_o : out std_logic;
WbWe_o : out std_logic; WbWe_o : out std_logic;
WbAdr_o : out std_logic_vector;
WbDat_o : out std_logic_vector;
WbAdr_o : out std_logic_vector(AddressWidth-1 downto 0);
WbDat_o : out std_logic_vector(DataWidth-1 downto 0);
--+ wishbone inputs --+ wishbone inputs
WbDat_i : in std_logic_vector;
WbDat_i : in std_logic_vector(DataWidth-1 downto 0);
WbAck_i : in std_logic; WbAck_i : in std_logic;
WbErr_i : in std_logic; WbErr_i : in std_logic;
--+ local register if --+ local register if
LocalWen_i : in std_logic; LocalWen_i : in std_logic;
LocalRen_i : in std_logic; LocalRen_i : in std_logic;
LocalAdress_i : in std_logic_vector;
LocalData_i : in std_logic_vector;
LocalData_o : out std_logic_vector;
LocalAdress_i : in std_logic_vector(AddressWidth-1 downto 0);
LocalData_i : in std_logic_vector(DataWidth-1 downto 0);
LocalData_o : out std_logic_vector(DataWidth-1 downto 0);
LocalAck_o : out std_logic; LocalAck_o : out std_logic;
LocalError_o : out std_logic LocalError_o : out std_logic
); );
@ -79,7 +84,7 @@ begin
--+ combinatoral local register if outputs --+ combinatoral local register if outputs
LocalData_o <= WbDat_i when s_wb_master_fsm = DATA else (LocalData_o'range => '0');
LocalData_o <= WbDat_i when s_wb_master_fsm = DATA else (others => '0');
LocalError_o <= WbErr_i when s_wb_master_fsm /= IDLE else '0'; LocalError_o <= WbErr_i when s_wb_master_fsm /= IDLE else '0';
LocalAck_o <= WbAck_i when (s_wb_master_fsm = ADDRESS or s_wb_master_fsm = DATA) and WbErr_i = '0' else '0'; LocalAck_o <= WbAck_i when (s_wb_master_fsm = ADDRESS or s_wb_master_fsm = DATA) and WbErr_i = '0' else '0';
@ -94,8 +99,8 @@ begin
begin begin
if(rising_edge(WbClk_i)) then if(rising_edge(WbClk_i)) then
if(WbRst_i = '1') then if(WbRst_i = '1') then
WbAdr_o <= (WbAdr_o'range => '0');
WbDat_o <= (WbDat_o'range => '0');
WbAdr_o <= (others => '0');
WbDat_o <= (others => '0');
s_wb_wen <= '0'; s_wb_wen <= '0';
else else
if (s_wb_master_fsm = IDLE) then if (s_wb_master_fsm = IDLE) then
@ -134,19 +139,21 @@ begin
-- report "WB master: Read error"; -- report "WB master: Read error";
-- PSL cover directives
CoverageG : if Coverage generate
-- psl COVER_LOCAL_WRITE : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
-- LocalRen_i = '0' and WbRst_i = '0'}
-- report "WB master: Local write";
--
-- psl COVER_LOCAL_READ : cover {s_wb_master_fsm = IDLE and LocalRen_i = '1' and
-- LocalWen_i = '0' and WbRst_i = '0'}
-- report "WB master: Local read";
--
-- psl COVER_LOCAL_WRITE_READ : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
-- LocalRen_i = '1' and WbRst_i = '0'}
-- report "WB master: Local write & read";
-- psl COVER_LOCAL_WRITE : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
-- LocalRen_i = '0' and WbRst_i = '0'}
-- report "WB master: Local write";
--
-- psl COVER_LOCAL_READ : cover {s_wb_master_fsm = IDLE and LocalRen_i = '1' and
-- LocalWen_i = '0' and WbRst_i = '0'}
-- report "WB master: Local read";
--
-- psl COVER_LOCAL_WRITE_READ : cover {s_wb_master_fsm = IDLE and LocalWen_i = '1' and
-- LocalRen_i = '1' and WbRst_i = '0'}
-- report "WB master: Local write & read";
end generate CoverageG;
end architecture rtl; end architecture rtl;

+ 13
- 9
syn/WishBoneSlaveE.vhd View File

@ -5,6 +5,10 @@ library ieee;
entity WishBoneSlaveE is entity WishBoneSlaveE is
generic (
AddressWidth : natural := 8;
DataWidth : natural := 8
);
port ( port (
--+ wishbone system if --+ wishbone system if
WbRst_i : in std_logic; WbRst_i : in std_logic;
@ -13,18 +17,18 @@ entity WishBoneSlaveE is
WbCyc_i : in std_logic; WbCyc_i : in std_logic;
WbStb_i : in std_logic; WbStb_i : in std_logic;
WbWe_i : in std_logic; WbWe_i : in std_logic;
WbAdr_i : in std_logic_vector;
WbDat_i : in std_logic_vector;
WbAdr_i : in std_logic_vector(AddressWidth-1 downto 0);
WbDat_i : in std_logic_vector(DataWidth-1 downto 0);
--+ wishbone outputs --+ wishbone outputs
WbDat_o : out std_logic_vector;
WbDat_o : out std_logic_vector(DataWidth-1 downto 0);
WbAck_o : out std_logic; WbAck_o : out std_logic;
WbErr_o : out std_logic; WbErr_o : out std_logic;
--+ local register if --+ local register if
LocalWen_o : out std_logic; LocalWen_o : out std_logic;
LocalRen_o : out std_logic; LocalRen_o : out std_logic;
LocalAdress_o : out std_logic_vector;
LocalData_o : out std_logic_vector;
LocalData_i : in std_logic_vector
LocalAdress_o : out std_logic_vector(AddressWidth-1 downto 0);
LocalData_o : out std_logic_vector(DataWidth-1 downto 0);
LocalData_i : in std_logic_vector(DataWidth-1 downto 0)
); );
end entity WishBoneSlaveE; end entity WishBoneSlaveE;
@ -75,11 +79,11 @@ begin
--+ local register if outputs --+ local register if outputs
LocalWen_o <= WbWe_i when s_wb_slave_fsm = ADDRESS and s_wb_active else '0'; LocalWen_o <= WbWe_i when s_wb_slave_fsm = ADDRESS and s_wb_active else '0';
LocalRen_o <= not(WbWe_i) when s_wb_slave_fsm = ADDRESS and s_wb_active else '0'; LocalRen_o <= not(WbWe_i) when s_wb_slave_fsm = ADDRESS and s_wb_active else '0';
LocalAdress_o <= WbAdr_i when s_wb_slave_fsm /= IDLE and s_wb_active else (LocalAdress_o'range => '0');
LocalData_o <= WbDat_i when s_wb_slave_fsm = ADDRESS and s_wb_active and WbWe_i = '1' else (LocalData_o'range => '0');
LocalAdress_o <= WbAdr_i when s_wb_slave_fsm /= IDLE and s_wb_active else (others => '0');
LocalData_o <= WbDat_i when s_wb_slave_fsm = ADDRESS and s_wb_active and WbWe_i = '1' else (others => '0');
--+ wishbone if outputs --+ wishbone if outputs
WbDat_o <= LocalData_i when s_wb_slave_fsm = DATA and WbWe_i = '0' else (WbDat_o'range => '0');
WbDat_o <= LocalData_i when s_wb_slave_fsm = DATA and WbWe_i = '0' else (others => '0');
WbAck_o <= '1' when s_wb_slave_fsm = DATA or (s_wb_slave_fsm = ADDRESS and s_wb_active and WbWe_i = '1') else '0'; WbAck_o <= '1' when s_wb_slave_fsm = DATA or (s_wb_slave_fsm = ADDRESS and s_wb_active and WbWe_i = '1') else '0';
WbErr_o <= '0'; WbErr_o <= '0';


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