tmeissner
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libvhdl
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5 Commits (9af05ea4af2b74014b6ec4316ee192787dcd19bf)

Author SHA1 Message Date
  T. Meissner 5dd42b80a2 add synthesizable and configurable SPI master component and enhance unit test 11 years ago
  T. Meissner dc24fc93b1 fixed reset initialisation of s_sclk_d 11 years ago
  T. Meissner 502aec376a replaced direct read from async SpiMosi_i input by read from registered a_mosi 11 years ago
  T. Meissner 308e33cd0c synthesis don't like the std_logic'val(int) construct, change to if/else instead 11 years ago
  T. Meissner c9fc7388c9 add synthesizable configurable SPI slave component and unit test 11 years ago
  T. Meissner ac5925c717 add synthesizable configurable SPI slave component and unit test 11 years ago