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libvhdl
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12 Commits (a21373945a826f55f934bbd0b0ce7183461b2ee8)

Author SHA1 Message Date
  T. Meissner f0e490142e moved register write into ADDRESS state, decreasing the write to one cycle only 10 years ago
  T. Meissner 285a25132e react to slave ack in ADDRESS state 10 years ago
  T. Meissner 7d60f0ae1b add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave 10 years ago
  T. Meissner c221b65074 ste is now generated combinatoral in parallel to the fsm 10 years ago
  T. Meissner 5c06158fac add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 10 years ago
  T. Meissner 034b10cdc9 change G_SCLK_DIVIDER range start to 6 (lowest working divider value) and adapt assertion to new range 10 years ago
  T. Meissner 5dd42b80a2 add synthesizable and configurable SPI master component and enhance unit test 10 years ago
  T. Meissner dc24fc93b1 fixed reset initialisation of s_sclk_d 10 years ago
  T. Meissner 502aec376a replaced direct read from async SpiMosi_i input by read from registered a_mosi 10 years ago
  T. Meissner 308e33cd0c synthesis don't like the std_logic'val(int) construct, change to if/else instead 10 years ago
  T. Meissner c9fc7388c9 add synthesizable configurable SPI slave component and unit test 10 years ago
  T. Meissner ac5925c717 add synthesizable configurable SPI slave component and unit test 10 years ago