tmeissner
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libvhdl
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2 Commits (a21373945a826f55f934bbd0b0ce7183461b2ee8)

Author SHA1 Message Date
  T. Meissner f0e490142e moved register write into ADDRESS state, decreasing the write to one cycle only 10 years ago
  T. Meissner 7d60f0ae1b add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave 10 years ago