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tmeissner
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libvhdl
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db5dfc76b0
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5 Commits (db5dfc76b05628e2e3a98f42535979b1b49baae1)
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T. Meissner
9af05ea4af
better comments, add report when wait_cycles() test finished
10 years ago
T. Meissner
3dd69f2d16
fixed stopping of clock when all tests are done
10 years ago
T. Meissner
cd72e16a7e
removed forgotten references to deleted StringP.vhd package
10 years ago
T. Meissner
389b3470f1
add cpha parameter do spi_master & spi_slave; change unit test to check all combinations of cpol & cpha
10 years ago
T. Meissner
58478fa5f0
add new SimP package with various general useful testbench procedures like spi master & slave
10 years ago