tmeissner
/
libvhdl
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Activity
Library of reusable VHDL components
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
134 Commits
2 Branches
914 KiB
 
 
 
Tree: 8e9b061a71
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '8e9b061a71'
${ noResults }
libvhdl/syn
T. Meissner 8e9b061a71 Use xor_reduce() of UtilsP package 4 years ago
..
SpiMasterE.vhd ste is now generated combinatoral in parallel to the fsm 10 years ago
SpiSlaveE.vhd add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 10 years ago
UartRx.vhd Use xor_reduce() of UtilsP package 4 years ago
UartTx.vhd Use xor_reduce() of UtilsP package 4 years ago
WishBoneCheckerE.vhd New Wishbone checks; Fix illegal PSL property 6 years ago
WishBoneMasterE.vhd Add bmc mode; integrate simulation PSL checks 5 years ago
WishBoneP.vhd Add bmc mode; integrate simulation PSL checks 5 years ago
WishBoneSlaveE.vhd Add bmc mode; integrate simulation PSL checks 5 years ago