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233 lines
6.9 KiB
233 lines
6.9 KiB
library ieee;
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use ieee.std_logic_1164.all;
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entity SpiMasterE is
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generic (
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G_DATA_WIDTH : positive := 8; --* data bus width
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G_SPI_CPOL : natural range 0 to 1 := 0; --* SPI clock polarity
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G_SPI_CPHA : natural range 0 to 1 := 0; --* SPI clock phase
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G_SCLK_DIVIDER : positive range 6 to positive'high := 10 --* SCLK divider related to system clock
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);
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port (
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--+ system if
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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--+ SPI slave if
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SpiSclk_o : out std_logic;
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SpiSte_o : out std_logic;
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SpiMosi_o : out std_logic;
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SpiMiso_i : in std_logic;
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--+ local VAI if
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Data_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_i : in std_logic;
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DataAccept_o : out std_logic;
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Data_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
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DataValid_o : out std_logic;
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DataAccept_i : in std_logic
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);
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end entity SpiMasterE;
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architecture rtl of SpiMasterE is
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type t_spi_state is (IDLE, WRITE, READ, CYCLE, STORE, SET_STE);
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signal s_spi_state : t_spi_state;
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signal s_send_register : std_logic_vector(G_DATA_WIDTH-1 downto 0);
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signal s_recv_register : std_logic_vector(G_DATA_WIDTH-1 downto 0);
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signal s_miso_d : std_logic_vector(1 downto 0);
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signal s_mosi : std_logic;
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signal s_sclk : std_logic;
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signal s_ste : std_logic;
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signal s_data_valid : std_logic;
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signal s_data_accept : std_logic;
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signal s_transfer_valid : boolean;
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signal s_sclk_rising : boolean;
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signal s_sclk_falling : boolean;
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signal s_read_edge : boolean;
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signal s_write_edge : boolean;
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alias a_miso : std_logic is s_miso_d(s_miso_d'left);
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begin
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--* Sync asynchronous SPI inputs with 2 stage FF line
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SpiSyncP : process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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s_miso_d <= (others => '0');
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elsif rising_edge(Clk_i) then
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s_miso_d <= s_miso_d(0) & SpiMiso_i;
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end if;
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end process SpiSyncP;
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--* Save local data input when new data is provided and
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--* we're not inside a running SPI transmission
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SendRegisterP : process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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s_send_register <= (others => '0');
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s_data_accept <= '0';
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elsif rising_edge(Clk_i) then
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s_data_accept <= '0';
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if (DataValid_i = '1' and s_spi_state = IDLE) then
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s_send_register <= Data_i;
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s_data_accept <= '1';
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end if;
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end if;
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end process SendRegisterP;
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--* Spi master control FSM
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SpiControlP : process (Reset_n_i, Clk_i) is
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variable v_bit_counter : natural range 0 to G_DATA_WIDTH-1;
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variable v_sclk_counter : natural range 0 to G_SCLK_DIVIDER-1;
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begin
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if (Reset_n_i = '0') then
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s_recv_register <= (others => '0');
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v_bit_counter := G_DATA_WIDTH-1;
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v_sclk_counter := G_SCLK_DIVIDER-1;
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s_transfer_valid <= false;
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s_ste <= '1';
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s_sclk <= std_logic'val(G_SPI_CPOL+2);
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s_mosi <= '1';
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s_spi_state <= IDLE;
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elsif rising_edge(Clk_i) then
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case s_spi_state is
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when IDLE =>
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s_ste <= '1';
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s_sclk <= std_logic'val(G_SPI_CPOL+2);
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s_mosi <= '0';
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s_recv_register <= (others => '0');
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v_bit_counter := G_DATA_WIDTH-1;
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v_sclk_counter := G_SCLK_DIVIDER/2-1;
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s_transfer_valid <= false;
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if(DataValid_i = '1' and s_data_accept = '1') then
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s_ste <= '0';
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s_spi_state <= WRITE;
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end if;
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when WRITE =>
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if (G_SPI_CPHA = 0 and v_bit_counter = G_DATA_WIDTH-1) then
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s_mosi <= s_send_register(v_bit_counter);
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s_spi_state <= READ;
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else
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if (v_sclk_counter = 0) then
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v_sclk_counter := G_SCLK_DIVIDER/2-1;
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s_sclk <= not(s_sclk);
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s_mosi <= s_send_register(v_bit_counter);
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s_spi_state <= READ;
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else
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v_sclk_counter := v_sclk_counter - 1;
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end if;
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end if;
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when READ =>
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if (v_sclk_counter = 0) then
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s_sclk <= not(s_sclk);
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s_recv_register(v_bit_counter) <= a_miso;
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v_sclk_counter := G_SCLK_DIVIDER/2-1;
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if (v_bit_counter = 0) then
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if (G_SPI_CPHA = 0) then
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s_spi_state <= CYCLE;
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else
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s_spi_state <= STORE;
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end if;
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else
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v_bit_counter := v_bit_counter - 1;
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s_spi_state <= WRITE;
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end if;
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else
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v_sclk_counter := v_sclk_counter - 1;
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end if;
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when CYCLE =>
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if (v_sclk_counter = 0) then
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s_sclk <= not(s_sclk);
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v_sclk_counter := G_SCLK_DIVIDER/2-1;
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s_spi_state <= STORE;
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else
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v_sclk_counter := v_sclk_counter - 1;
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end if;
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when STORE =>
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if (v_sclk_counter = 0) then
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s_transfer_valid <= true;
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v_sclk_counter := G_SCLK_DIVIDER/2-1;
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s_spi_state <= SET_STE;
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else
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v_sclk_counter := v_sclk_counter - 1;
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end if;
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when SET_STE =>
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s_transfer_valid <= false;
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s_ste <= '1';
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if (v_sclk_counter = 0) then
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s_spi_state <= IDLE;
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else
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v_sclk_counter := v_sclk_counter - 1;
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end if;
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when others =>
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s_spi_state <= IDLE;
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end case;
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end if;
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end process SpiControlP;
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--* Provide received SPI data to local interface
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--* Output data is overwritten if it isn't fetched
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--* until next finished SPI transmission
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RecvRegisterP : process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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Data_o <= (others => '0');
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s_data_valid <= '0';
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elsif rising_edge(Clk_i) then
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if (s_transfer_valid) then
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Data_o <= s_recv_register;
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s_data_valid <= '1';
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end if;
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if (DataAccept_i = '1' and s_data_valid = '1') then
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s_data_valid <= '0';
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end if;
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end if;
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end process RecvRegisterP;
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--+ Output port connections
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DataValid_o <= s_data_valid;
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DataAccept_o <= s_data_accept;
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SpiSte_o <= s_ste;
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SpiSclk_o <= s_sclk;
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SpiMosi_o <= s_mosi;
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assert G_SCLK_DIVIDER rem 2 = 0
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report "WARNING: " & SpiMasterE'instance_name & LF & "G_SCLK_DIVIDER " & integer'image(G_SCLK_DIVIDER) &
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" rounded down to next even value " & integer'image(G_SCLK_DIVIDER-1)
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severity warning;
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-- psl default clock is rising_edge(Clk_i);
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--
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-- psl assert always (s_spi_state = IDLE or s_spi_state = WRITE or s_spi_state = READ or
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-- s_spi_state = CYCLE or s_spi_state = SET_STE or s_spi_state = STORE);
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-- psl assert always (s_data_valid and DataAccept_i) -> next not(s_data_valid);
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end architecture rtl;
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