tmeissner/libvhdl: Library of reusable VHDL components - libvhdl - goodcleanfun Gitea

Library of reusable VHDL components

vhdl ghdl osvvm psl fpga testbenches coverage

History

T. Meissner c1005badfc Add PSL assertions to check initiating of WishBone write/read transfer WB_WRITE & WB_READ check that a write/read transfer is started on the WishBone bus if requested on the local port of the WishBoneMasterE unit at the adequate time.		9 years ago
..
SpiMasterE.vhd	ste is now generated combinatoral in parallel to the fsm	10 years ago
SpiSlaveE.vhd	add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa	10 years ago
WishBoneMasterE.vhd	Add PSL assertions to check initiating of WishBone write/read transfer	9 years ago
WishBoneSlaveE.vhd	Fix PSL assertions for local wen and local ren	9 years ago