Library of reusable VHDL components
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T. Meissner cf1798b576 Guard test for value with to_ux01() function 5 years ago
common Guard test for value with to_ux01() function 5 years ago
sim Make proc/fnc input parameters constant 6 years ago
syn Add PSL assertions to check initiating of WishBone write/read transfer 6 years ago
test Replace directed Wishbone tests by coverage driven ones 5 years ago
.gitignore add gitignore file 7 years ago
LICENSE.md Changed from LGPLv3 to OHDL license 6 years ago
README.md Add info about common/UtilsP package 6 years ago

README.md

libvhdl

A OHDL licensed library of reusable components for VHDL designs and testbenches

##sim (Non) synthesible components for testbenches

AssertP

Package with various assertion procedures.

  • assert_true(x[, str, level]) checks if boolean x = false
  • assert_false(x[, str, level]) checks if boolean x = false
  • assert_equal(x, y[, str, level]) checks if x = y
  • assert_unequal(x, y[, str, level]) checks if x /= y

All of the assert_* procedures have following optional parameters:

  • str print string str to console instead implemented one
  • level severity level (note, warning, error, failure)
SimP

Package with various components general useful for simulation

  • wait_cycles(x, n) waits for n rising edges on std_logic signal x
  • spi_master() configurable master for SPI protocol, supports all cpol/cpha modes
  • spi_slave() configurable slave for SPI protocol, supports all cpol/cpha modes
QueueP

Package with various implementations of queue types:

  • t_simple_queue simple array based FIFO queue
  • t_list_queue linked list FIFO queue using access types
DictP

Package with implementation of dictionary (aka associative array) type:

  • t_dict linked list dictionary using access types

syn

Synthesizable components for implementing in FPGA

SpiMasterE

Configurable SPI master with support modes 0-3 and simple VAI local backend.

SpiSlaveE

Configurable SPI slave with support modes 0-3 and simple VAI local backend.

WishBoneMasterE

Simple WishBone bus master with support of classic single write & read

WishBoneSlaveE

Simple WishBone bus slave with support of classic single write & read and register backend

##test Unit tests for each component

QueueT

Unit tests for components of QueueP package

SimT

Unit tests for components of SimP package

SpiT

Unit tests for SpiMasterE and SpiSlaveE components

WishBoneT

Unit tests for WishBoneMasterE and WishBoneSlaveE components

common

Common utilities

UtilsP

Common functions useful for simulation/synthesis

  • and_reduce(x) returns and of all items in x, collapsed to one std_logic/boolean
  • or_reduce(x) returns or of all items in x, collapsed to one std_logic/boolean
  • xor_reduce(x) returns xor of items in x, collapsed to one std_logic
  • even_parity(x) returns even parity of x
  • odd_parity(x) returns odd parity of x
  • count_ones(x) returns number of '1' in x
  • one_hot(x) returns true if x is one-hot coded, false otherwise
  • is_unknown(x) returns true if x contains 'U' bit, false otherwise
  • uint_to_slv(x, l) returns std_logic_vector (unsigned) with length l converted from x (natural)
  • slv_to_uint(x) returns natural converted from x (std_logic_vector) (unsigned)
  • uint_bitsize(x) returns number of bits needed for given x (natural)

Dependencies

To run the tests, you have to install GHDL. You can get it from http://sourceforge.net/projects/ghdl-updates/.

If you use the 0.31 version of GHDL, you need the VHDL-2008 proposed packages because libvhdl uses various VHDL-2008 features. To get the needed files, you can use the get_vhdl_2008.sh script which downloads the files into the vhdl_2008 folder and patches the env_c.vhdl file to get in compiled with GHDL.

If you build GHDL from actual source or use another simulator with VHDL-2008 support, you don't need these packages. Instead you have to outcomment the references to these packages from the source files.

libvhdl also uses the OSVVM library to generate random data for the unit tests. We use version OSVVM version 2014.01. You can find it under the OSVVM folder in the test/ directory. If you use another simulator with full OSVVM support, you can download newer versions of the library from http://osvvm.org.

Another useful tool is GTKWave, install it if you want to use the waveform files generated by some of the tests.

Building

Type make to do all tests. You should see the successfully running tests like this:

$ make
ghdl -a --std=02 ../sim/QueueP.vhd QueueT.vhd
ghdl -e --std=02 QueueT
ghdl -r --std=02 QueueT
QueueT.vhd:52:5:@0ms:(report note): INFO: t_simple_queue test finished successfully
QueueT.vhd:87:5:@0ms:(report note): INFO: t_list_queue test finished successfully