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80 lines
2.0 KiB
80 lines
2.0 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library libvhdl;
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use libvhdl.AssertP.all;
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use libvhdl.QueueP.all;
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entity QueueT is
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end entity QueueT;
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architecture sim of QueueT is
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constant C_QUEUE_DEPTH : natural := 64;
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shared variable sv_simple_queue : t_simple_queue;
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shared variable sv_list_queue : t_list_queue;
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begin
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QueueInitP : process is
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begin
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sv_list_queue.init(C_QUEUE_DEPTH);
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wait;
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end process QueueInitP;
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SimpleQueueTestP : process is
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variable v_data : std_logic_vector(63 downto 0);
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begin
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-- check initial emptiness
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assert_true(sv_simple_queue.is_empty, "Queue should be empty!");
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for i in 0 to 63 loop
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sv_simple_queue.push(std_logic_vector(to_unsigned(i, 64)));
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end loop;
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-- check that it's full
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assert_true(sv_simple_queue.is_full, "Queue should be full!");
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-- empty the queue
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for i in 0 to 63 loop
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sv_simple_queue.pop(v_data);
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assert_equal(v_data, std_logic_vector(to_unsigned(i, 64)));
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end loop;
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-- check emptiness
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assert_true(sv_simple_queue.is_empty, "Queue should be empty!");
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report "INFO: t_simple_queue test finished successfully";
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wait;
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end process SimpleQueueTestP;
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ListQueueTestP : process is
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variable v_data : std_logic_vector(7 downto 0);
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begin
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-- check initial emptiness
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assert_true(sv_list_queue.is_empty, "Queue should be empty!");
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for i in 0 to C_QUEUE_DEPTH-1 loop
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sv_list_queue.push(std_logic_vector(to_unsigned(i, 8)));
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end loop;
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-- check that it's full
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assert_equal(sv_list_queue.fillstate, C_QUEUE_DEPTH, "Queue should have" & integer'image(C_QUEUE_DEPTH) & "entries");
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-- empty the queue
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for i in 0 to C_QUEUE_DEPTH-1 loop
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sv_list_queue.pop(v_data);
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assert_equal(v_data, std_logic_vector(to_unsigned(i, 8)));
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end loop;
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-- check emptiness
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assert_true(sv_list_queue.is_empty, "Queue should be empty!");
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report "INFO: t_list_queue test finished successfully";
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wait;
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end process ListQueueTestP;
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end architecture sim;
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