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@ -0,0 +1,48 @@ |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use work.pkg.all; |
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entity psl_next_event is |
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port ( |
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clk : in std_logic |
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); |
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end entity psl_next_event; |
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architecture psl of psl_next_event is |
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signal a, b, c : std_logic; |
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signal d, e, f : std_logic; |
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begin |
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-- 012345678901234 |
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SEQ_A : sequencer generic map ("_-________-____") port map (clk, a); |
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SEQ_B : sequencer generic map ("____-_-____-__-") port map (clk, b); |
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SEQ_C : sequencer generic map ("____-______-___") port map (clk, c); |
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-- 012345678901234 |
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SEQ_D : sequencer generic map ("_-______-_-____") port map (clk, d); |
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SEQ_E : sequencer generic map ("____-_-_--_-__-") port map (clk, e); |
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SEQ_F : sequencer generic map ("____-___-__-___") port map (clk, f); |
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-- All is sensitive to rising edge of clk |
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default clock is rising_edge(clk); |
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-- This assertion holds |
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NEXT_EVENT_0_a : assert always (a -> next_event(b)(c)); |
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-- This assertion holds |
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NEXT_EVENT_1_a : assert always (d -> next_event(e)(f)); |
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-- This assertion holds |
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NEXT_EVENT_2_a : assert always (a -> next next_event(b)(c)); |
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-- This assertion doesn't hold at cycle 9 |
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NEXT_EVENT_3_a : assert always (d -> next next_event(e)(f)); |
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end architecture psl; |