Add example for SERE fusion (:) operator

README.md

@@ -46,6 +46,7 @@ The next lists will grow during further development
 ### Sequential Extended Regular Expressions (SERE style)
 
 * Simple SERE
+* Fusion operator (`:`)
 * Overlapping suffix implication operator (`|->`)
 * Non overlapping suffix implication operator (`|=>`)
 * Consecutive repetition operator (`[*]`, `[+]`, `[*n]`, `[*i to j]`)

formal/psl_sere_fusion.sby

@@ -0,0 +1,18 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_fusion.vhd -e psl_sere_fusion
+prep -top psl_sere_fusion
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_fusion.vhd

formal/tests.mk

@@ -24,4 +24,5 @@ psl_sere_within \
 psl_sere_or \
 psl_sere_len_matching_and \
 psl_sere_non_len_matching_and \
+psl_sere_fusion \
 psl_prev

sim/tests.mk

@@ -23,4 +23,5 @@ psl_cover \
 psl_sere_within \
 psl_sere_or \
 psl_sere_len_matching_and \
-psl_sere_non_len_matching_and
+psl_sere_non_len_matching_and \
+psl_sere_fusion

src/psl_sere_fusion.vhd

@@ -0,0 +1,46 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_fusion is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_fusion;
+
+
+architecture psl of psl_sere_fusion is
+
+  signal req, avalid, busy, adone, data, ddone : std_logic;
+
+begin
+
+
+  --                                   0123456789012
+  SEQ_REQ    : sequencer generic map ("_-___________") port map (clk, req);
+  SEQ_AVALID : sequencer generic map ("__-__________") port map (clk, avalid);
+  SEQ_BUSY   : sequencer generic map ("___-_--______") port map (clk, busy);
+  SEQ_ADONE  : sequencer generic map ("_______-_____") port map (clk, adone);
+  SEQ_DATA   : sequencer generic map ("_______---___") port map (clk, data);
+  SEQ_DDONE  : sequencer generic map ("__________-__") port map (clk, ddone);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- SERE fusion operator
+  -- SERE fusion is like concatenation (;) but starts at
+  -- the same cycle that the LHS ends
+  -- This assertion holds
+  SERE_0_a : assert always {req} |=> {{avalid; busy[->3]; adone} : {data[->3]; ddone}};
+
+  -- Stop simulation after longest running sequencer is finished
+  -- Simulation only code by using pragmas
+  -- synthesis translate_off
+  stop_sim(clk, 13);
+  -- synthesis translate_on
+
+
+end architecture psl;