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@ -67,8 +67,8 @@ begin |
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-- to see if your assertions can actually be active. |
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-- This assertion checks for the final done at the end of transfer. |
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-- In cover mode, the LHS side of the property has to hold. |
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-- This cover directive holds at cycle 6 |
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ASSERT_a : assert always {req; {{busy[=3]} && {not done[+]}}} |=> {done}; |
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-- This cover directive holds at cycle 7 |
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ASSERT_a : assert always {req; (busy and not done)[=3]; not done} |=> {done}; |
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end architecture psl; |