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Fixed assertion - combining SEREs isn't trivial ;)

master
T. Meissner 5 years ago
parent
commit
4dd0f1b33c
1 changed files with 2 additions and 2 deletions
  1. +2
    -2
      src/psl_cover.vhd

+ 2
- 2
src/psl_cover.vhd View File

@ -67,8 +67,8 @@ begin
-- to see if your assertions can actually be active.
-- This assertion checks for the final done at the end of transfer.
-- In cover mode, the LHS side of the property has to hold.
-- This cover directive holds at cycle 6
ASSERT_a : assert always {req; {{busy[=3]} && {not done[+]}}} |=> {done};
-- This cover directive holds at cycle 7
ASSERT_a : assert always {req; (busy and not done)[=3]; not done} |=> {done};
end architecture psl;

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