Add examples for onehot() & onehot0() PSL functions

README.md

@@ -65,6 +65,8 @@ The next lists will grow during further development
 * `stable()` function (Synthesis only)
 * `rose()` function (Synthesis only)
 * `fell()` function (Synthesis only)
+* `onehot()` function (Synthesis only)
+* `onehot0()` function (Synthesis only)
 
 ### Convenient stuff
 
@@ -85,7 +87,7 @@ The next lists will grow during further development
 * `forall` operator
 * `for` operator
 * Synthesis of strong operator versions
-* PSL functions (`prev()`, `stable()`,`rose()` & `fell()` are implemented for synthesis)
+* PSL functions (`prev()`, `stable()`,`rose()`, `fell()`, `onehot()` & `onehot0()` are implemented for synthesis)
 * PSL macros (`%for`, `%if`)
 
 ## Under investigation

formal/psl_onehot.sby

@@ -0,0 +1,19 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd hex_sequencer.vhd psl_onehot.vhd -e psl_onehot
+prep -top psl_onehot
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/hex_sequencer.vhd
+../src/psl_onehot.vhd

formal/psl_onehot0.sby

@@ -0,0 +1,19 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd hex_sequencer.vhd psl_onehot0.vhd -e psl_onehot0
+prep -top psl_onehot0
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/hex_sequencer.vhd
+../src/psl_onehot0.vhd

src/psl_onehot.vhd

@@ -0,0 +1,42 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_onehot is
+  port (
+    clk : in std_logic
+  );
+end entity psl_onehot;
+
+
+architecture psl of psl_onehot is
+
+  signal a, b : std_logic_vector(3 downto 0);
+
+begin
+
+
+  --                                  012345678901234
+  SEQ_A : hex_sequencer generic map ("111222444888888") port map (clk, a);
+  SEQ_B : hex_sequencer generic map ("111222444888999") port map (clk, b);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  ONEHOT_0_a : assert always onehot(a);
+
+  -- This assertion fails at cycle 12
+  ONEHOT_1_a : assert always onehot(b);
+
+  -- Stop simulation after longest running sequencer is finished
+  -- Simulation only code by using pragmas
+  -- synthesis translate_off
+  stop_sim(clk, 15);
+  -- synthesis translate_on
+
+
+end architecture psl;

src/psl_onehot0.vhd

@@ -0,0 +1,42 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_onehot0 is
+  port (
+    clk : in std_logic
+  );
+end entity psl_onehot0;
+
+
+architecture psl of psl_onehot0 is
+
+  signal a, b : std_logic_vector(3 downto 0);
+
+begin
+
+
+  --                                  012345678901234567
+  SEQ_A : hex_sequencer generic map ("000111222444888888") port map (clk, a);
+  SEQ_B : hex_sequencer generic map ("000111222444888fff") port map (clk, b);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  ONEHOT0_0_a : assert always onehot0(a);
+
+  -- This assertion fails at cycle 15
+  ONEHOT0_1_a : assert always onehot0(b);
+
+  -- Stop simulation after longest running sequencer is finished
+  -- Simulation only code by using pragmas
+  -- synthesis translate_off
+  stop_sim(clk, 20);
+  -- synthesis translate_on
+
+
+end architecture psl;