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@ -79,7 +79,7 @@ package body pkg is |
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-- synthesis translate_off |
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procedure stop_sim (signal clk : in std_logic; cycles : in natural; add_cycles : in natural := 2) is |
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variable index : natural := cycles + 5; |
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variable index : natural := cycles + add_cycles; |
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begin |
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loop |
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wait until rising_edge(clk); |
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@ -88,7 +88,7 @@ package body pkg is |
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exit; |
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end if; |
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end loop; |
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stop(0); |
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finish(0); |
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end procedure stop_sim; |
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-- synthesis translate_on |
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