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@ -30,12 +30,12 @@ begin |
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default clock is rising_edge(clk); |
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default clock is rising_edge(clk); |
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-- This assertion holds |
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-- This assertion holds |
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STABLE_0_a : assert always {not valid; valid} -> next (stable(a) until_ ack); |
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STABLE_0_a : assert always {not valid; valid} |=> (stable(a) until_ ack); |
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-- This assertion holds |
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-- This assertion holds |
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STABLE_1_a : assert always {not valid; valid} -> next (stable(b) until_ ack); |
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STABLE_1_a : assert always {not valid; valid} |=> (stable(b) until_ ack); |
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-- Workaround needed before stable() is implemented |
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-- Workaround needed before stable() was implemented |
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-- With VHDL glue logic generating the |
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-- With VHDL glue logic generating the |
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-- previous value of a and simple comparing the two values |
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-- previous value of a and simple comparing the two values |
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a_reg : block is |
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a_reg : block is |
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