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@ -14,6 +14,8 @@ end entity psl_sere_consecutive_repetition; |
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architecture psl of psl_sere_consecutive_repetition is |
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signal a, b, c : std_logic; |
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signal d, e, f : std_logic; |
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signal g, h, i : std_logic; |
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begin |
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@ -23,6 +25,16 @@ begin |
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SEQ_B : sequencer generic map ("__----___") port map (clk, b); |
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SEQ_C : sequencer generic map ("______-__") port map (clk, c); |
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-- 012345 |
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SEQ_D : sequencer generic map ("_-____") port map (clk, d); |
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SEQ_E : sequencer generic map ("______") port map (clk, e); |
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SEQ_F : sequencer generic map ("__-___") port map (clk, f); |
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-- 012345678 |
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SEQ_G : sequencer generic map ("_-_______") port map (clk, g); |
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SEQ_H : sequencer generic map ("__-_-_-__") port map (clk, h); |
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SEQ_I : sequencer generic map ("_______-_") port map (clk, i); |
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-- All is sensitive to rising edge of clk |
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default clock is rising_edge(clk); |
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@ -42,5 +54,26 @@ begin |
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-- This assertion holds |
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SERE_4_a : assert always {a} |=> {b[+]; c}; |
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-- This assertion holds |
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SERE_5_a : assert always {d} |=> {e[*]; f}; |
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-- This assertion doesn't hold at cycle 2 |
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SERE_6_a : assert always {d} |=> {e[+]; f}; |
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-- This assertion doesn't hold at cycle 3 |
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SERE_7_a : assert always {g} |=> {h[*3]; i}; |
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-- This assertion doesn't hold at cycle 3 |
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SERE_8_a : assert always {g} |=> {h[*2 to 4]; i}; |
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-- This assertion doesn't hold at cycle 3 |
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SERE_9_a : assert always {g} |=> {h[*]; i}; |
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-- This assertion doesn't hold at cycle 3 |
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SERE_10_a : assert always {g} |=> {h[+]; i}; |
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-- This assertion holds |
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SERE_11_a : assert always {g} |=> {[*5]; i}; |
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end architecture psl; |