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@ -16,6 +16,9 @@ architecture psl of psl_next_a is |
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signal a, b : std_logic; |
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signal c, d : std_logic; |
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signal e, f : std_logic; |
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signal g, h : std_logic; |
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signal i, j : std_logic; |
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signal k, l : std_logic; |
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begin |
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@ -32,6 +35,18 @@ begin |
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SEQ_E : sequencer generic map ("__-_-______") port map (clk, e); |
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SEQ_F : sequencer generic map ("_____-----_") port map (clk, f); |
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-- 01234567890 |
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SEQ_G : sequencer generic map ("__-_-______") port map (clk, g); |
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SEQ_H : sequencer generic map ("_____-_---_") port map (clk, h); |
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-- 012345678901 |
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SEQ_I : sequencer generic map ("__-_-_______") port map (clk, i); |
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SEQ_J : sequencer generic map ("_____-__-___") port map (clk, j); |
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-- 0123456789 |
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SEQ_K : sequencer generic map ("__-_-_____") port map (clk, k); |
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SEQ_L : sequencer generic map ("_______-__") port map (clk, l); |
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-- All is sensitive to rising edge of clk |
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default clock is rising_edge(clk); |
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@ -45,5 +60,14 @@ begin |
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-- This assertion holds |
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NEXT_2_a : assert always (e -> next_a[3 to 5] (f)); |
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-- This assertion doesn't hold at cycle 6 |
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NEXT_3_a : assert always (g -> next_a[3 to 5] (h)); |
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-- This assertion doesn't hold at cycle 6 |
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NEXT_4_a : assert always (i -> next_a[3 to 5] (j)); |
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-- This assertion doesn't hold at cycle 5 |
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NEXT_5_a : assert always (k -> next_a[3 to 5] (l)); |
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end architecture psl; |