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@ -25,8 +25,17 @@ begin |
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-- All is sensitive to rising edge of clk |
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default clock is rising_edge(clk); |
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-- Beware: potential pitfall! |
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-- Every time a PSL assertion is similar to a concurrent |
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-- VHDL assertion at that place, it is interpreted as such |
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-- This assert is considered as VHDL assert statement, |
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-- so it is active every cycle |
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-- This assertion doesn't hold at cycle 2 |
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VHDL_ASSERT_a : assert a; |
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-- The PSL comment helps to mark this as PSL assert |
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-- This assertion holds |
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WITHOUT_ALWAYS_a : assert a; |
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-- psl WITHOUT_ALWAYS_a : assert a; |
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-- This assertion doesn't hold at cycle 2 |
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WITH_ALWAYS_a : assert always a; |
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