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Add issue code for PSL endpoints used in inline mode (ghdl/ghdl#1378)

T. Meissner 2 weeks ago
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1 changed files with 98 additions and 0 deletions
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      issues/issue_1378.vhd

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issues/issue_1378.vhd View File

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+library ieee;
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+  use ieee.std_logic_1164.all;
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+
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+
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+entity sequencer is
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+  generic (
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+    seq : string
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+  );
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+  port (
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+    clk  : in  std_logic;
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+    data : out std_logic
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+  );
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+end entity sequencer;
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+
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+
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+architecture rtl of sequencer is
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+
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+  signal index : natural := seq'low;
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+
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+  function to_bit (a : in character) return std_logic is
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+    variable ret : std_logic;
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+  begin
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+    case a is
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+      when '0' | '_' => ret := '0';
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+      when '1' | '-' => ret := '1';
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+      when others    => ret := 'X';
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+    end case;
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+    return ret;
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+  end function to_bit;
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+
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+begin
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+
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+  process (clk) is
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+  begin
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+    if rising_edge(clk) then
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+      if (index < seq'high) then
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+        index <= index + 1;
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+      end if;
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+    end if;
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+  end process;
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+
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+  data <= to_bit(seq(index));
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+
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+end architecture rtl;
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+
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+
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+library ieee;
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+  use ieee.std_logic_1164.all;
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+
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+
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+library ieee;
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+  use ieee.std_logic_1164.all;
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+  use ieee.numeric_std.all;
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+
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+
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+entity issue is
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+  port (
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+    clk : in std_logic
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+  );
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+end entity issue;
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+
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+
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+architecture psl of issue is
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+
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+  component sequencer is
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+    generic (
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+      seq : string
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+    );
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+    port (
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+      clk  : in  std_logic;
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+      data : out std_logic
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+    );
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+  end component sequencer;
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+
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+  signal a, b, c : std_logic;
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+
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+begin
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+
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+  --                              01234567890123
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+  SEQ_A : sequencer generic map ("_-_____-______") port map (clk, a);
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+  SEQ_B : sequencer generic map ("__--____---___") port map (clk, b);
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+  SEQ_C : sequencer generic map ("____-______-__") port map (clk, c);
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+
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+
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+  -- All is sensitive to rising edge of clk
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+  default clock is rising_edge(clk);
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+
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+  -- Doesn't work with inline PSL
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+  -- endpoint ENDPOINT_0_e is {a; b[*2]; c};
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+
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+  -- endpoint in psl comment works
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+  -- psl endpoint ENDPOINT_1_e is {a; b[*3]; c};
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+
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+  assert not ENDPOINT_1_e
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+    report "Endpoint hit"
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+    severity note;
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+
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+end architecture psl;