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130 lines
2.1 KiB
130 lines
2.1 KiB
library ieee;
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use ieee.std_logic_1164.all;
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entity sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic
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);
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end entity sequencer;
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architecture rtl of sequencer is
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signal index : natural := seq'low;
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function to_bit (a : in character) return std_logic is
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variable ret : std_logic;
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begin
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case a is
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when '0' | '_' => ret := '0';
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when '1' | '-' => ret := '1';
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when others => ret := 'X';
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end case;
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return ret;
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end function to_bit;
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if (index < seq'high) then
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index <= index + 1;
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end if;
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end if;
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end process;
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data <= to_bit(seq(index));
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end architecture rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity issue is
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port (
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clk : in std_logic
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);
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end entity issue;
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architecture psl of issue is
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component sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic
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);
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end component sequencer;
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signal a, b : std_logic;
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begin
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-- 0123456789012345
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SEQ_A : sequencer generic map ("__-__-____-_____") port map (clk, a);
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SEQ_B : sequencer generic map ("_______-________") port map (clk, b);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion should fail
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EVENTUALLY_a : assert always (a -> eventually! b);
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end architecture psl;
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library ieee;
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use ieee.std_logic_1164.all;
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use std.env.all;
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entity test_issue is
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end entity test_issue;
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architecture sim of test_issue is
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signal clk : std_logic := '1';
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begin
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clk <= not clk after 500 ps;
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DUT : entity work.issue(psl) port map (clk);
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-- stop simulation after 30 cycles
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process
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variable index : natural := 29;
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begin
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loop
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wait until rising_edge(clk);
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index := index - 1;
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exit when index = 0;
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end loop;
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stop(0);
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-- finish(0);
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end process;
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end architecture sim;
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