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61 lines
1.8 KiB
61 lines
1.8 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_abort is
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port (
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clk : in std_logic
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);
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end entity psl_abort;
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architecture psl of psl_abort is
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signal a, b, c, d : std_logic;
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begin
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-- Creating an abort signal which is asynchronously set & reset
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d <= '0', '1' after 1100 ps, '0' after 1400 ps;
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-- 0123456789
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SEQ_A : sequencer generic map ("-___-_____") port map (clk, a);
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SEQ_B : sequencer generic map ("_______-__") port map (clk, b);
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SEQ_C : sequencer generic map ("-_________") port map (clk, c);
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-- D : _|________
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion doesn't hold at cycle 4
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WITHOUT_ABORT_a : assert (always a -> next (b before a));
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-- This assertion holds
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WITH_ABORT_0_a : assert (always a -> next (b before a)) abort c;
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-- In simulation this assertion should also hold, but it does not
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-- GHDL seemed to implement abort as sync_abort instead of async_abort
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-- See 1850-2010 6.2.1.5.1 abort, async_abort and sync_abort
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-- In formal this assertion fails at cycle 4 as d is 0 all the time
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-- Is fixed now, see issue ghdl/ghdl#1654
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WITH_ABORT_1_a : assert (always a -> next (b before a)) abort d;
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-- async_abort is similar to abort
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-- In formal this assertion fails at cycle 4 as d is 0 all the time
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WITH_ABORT_2_a : assert (always a -> next (b before a)) async_abort d;
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-- sync_abort is working on synchronously events
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-- This assertion holds
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WITH_ABORT_3_a : assert (always a -> next (b before a)) sync_abort c;
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 12);
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-- synthesis translate_on
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end architecture psl;
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