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40 lines
869 B
40 lines
869 B
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_eventually is
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port (
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clk : in std_logic
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);
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end entity psl_eventually;
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architecture psl of psl_eventually is
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signal a, b : std_logic;
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begin
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-- 0123456789012345
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SEQ_A : sequencer generic map ("__-__-____-_____") port map (clk, a);
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SEQ_B : sequencer generic map ("_______-______-_") port map (clk, b);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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-- This assertion leads to a GHDL synthesis crash with bug report
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EVENTUALLY_a : assert always (a -> eventually! b);
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 16);
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-- synthesis translate_on
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end architecture psl;
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