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53 lines
1.4 KiB
53 lines
1.4 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_logical_implication is
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port (
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clk : in std_logic
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);
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end entity psl_logical_implication;
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architecture psl of psl_logical_implication is
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signal a, b, c, d : std_logic;
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begin
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-- 01234567890
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SEQ_A : sequencer generic map ("_-__-___-__") port map (clk, a);
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SEQ_B : sequencer generic map ("_-______-__") port map (clk, b);
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SEQ_C : sequencer generic map ("_-__-______") port map (clk, c);
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SEQ_D : sequencer generic map ("___________") port map (clk, d);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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IMPLICATION_0_a : assert always (a -> b or c);
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-- This assertion doesn't hold at cycle 4
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IMPLICATION_1_a : assert always (a -> b and c);
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-- This assertion holds because RHS of implication always holds
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IMPLICATION_2_a : assert always (a -> true);
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-- This assertion doesn't hold at cycle 1 because RHS of implication never holds
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IMPLICATION_3_a : assert always (a -> false);
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-- This assertion holds because LHS of implication never holds
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IMPLICATION_4_a : assert always (d -> (a and b and c));
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 11);
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-- synthesis translate_on
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end architecture psl;
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