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47 lines
1.0 KiB
47 lines
1.0 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_next is
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port (
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clk : in std_logic
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);
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end entity psl_next;
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architecture psl of psl_next is
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signal a, b : std_logic;
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signal c, d : std_logic;
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begin
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-- 012345678901
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SEQ_A : sequencer generic map ("_-__--__-__") port map (clk, a);
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SEQ_B : sequencer generic map ("_--__--__--") port map (clk, b);
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-- 012345678901
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SEQ_C : sequencer generic map ("_-__--__-__") port map (clk, c);
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SEQ_D : sequencer generic map ("_--__-___--") port map (clk, d);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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NEXT_0_a : assert always (a -> next b);
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-- This assertion doesn't hold at cycle 6
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NEXT_1_a : assert always (c -> next d);
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 12);
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-- synthesis translate_on
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end architecture psl;
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