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55 lines
1.3 KiB
55 lines
1.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_next_3 is
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port (
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clk : in std_logic
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);
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end entity psl_next_3;
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architecture psl of psl_next_3 is
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signal a, b : std_logic;
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signal c, d : std_logic;
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signal e, f : std_logic;
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begin
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-- 01234567890
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SEQ_A : sequencer generic map ("__-_-______") port map (clk, a);
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SEQ_B : sequencer generic map ("_____-_-___") port map (clk, b);
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-- 01234567890
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SEQ_C : sequencer generic map ("__-_-______") port map (clk, c);
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SEQ_D : sequencer generic map ("_____-_____") port map (clk, d);
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-- 01234567890
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SEQ_E : sequencer generic map ("__-_-______") port map (clk, e);
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SEQ_F : sequencer generic map ("_____-----_") port map (clk, f);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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NEXT_0_a : assert always (a -> next[3] (b));
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-- This assertion doesn't hold at cycle 7
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NEXT_1_a : assert always (c -> next[3] (d));
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-- This assertion holds
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NEXT_2_a : assert always (e -> next[3] (f));
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 11);
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-- synthesis translate_on
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end architecture psl;
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