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46 lines
1.3 KiB
46 lines
1.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere_fusion is
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port (
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clk : in std_logic
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);
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end entity psl_sere_fusion;
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architecture psl of psl_sere_fusion is
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signal req, avalid, busy, adone, data, ddone : std_logic;
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begin
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-- 0123456789012
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SEQ_REQ : sequencer generic map ("_-___________") port map (clk, req);
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SEQ_AVALID : sequencer generic map ("__-__________") port map (clk, avalid);
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SEQ_BUSY : sequencer generic map ("___-_--______") port map (clk, busy);
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SEQ_ADONE : sequencer generic map ("_______-_____") port map (clk, adone);
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SEQ_DATA : sequencer generic map ("_______---___") port map (clk, data);
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SEQ_DDONE : sequencer generic map ("__________-__") port map (clk, ddone);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- SERE fusion operator
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-- SERE fusion is like concatenation (;) but starts at
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-- the same cycle that the LHS ends
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-- This assertion holds
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SERE_0_a : assert always {req} |=> {{avalid; busy[->3]; adone} : {data[->3]; ddone}};
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 13);
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-- synthesis translate_on
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end architecture psl;
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