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44 lines
1.2 KiB
44 lines
1.2 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere_len_matching_and is
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port (
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clk : in std_logic
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);
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end entity psl_sere_len_matching_and;
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architecture psl of psl_sere_len_matching_and is
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signal req, busy, valid, done : std_logic;
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begin
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-- 0123456789
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SEQ_REQ : sequencer generic map ("_-________") port map (clk, req);
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SEQ_BUSY : sequencer generic map ("__------__") port map (clk, busy);
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SEQ_VALID : sequencer generic map ("___-_-_-__") port map (clk, valid);
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SEQ_DONE : sequencer generic map ("________-_") port map (clk, done);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Length matching AND two SERE
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-- valid has to hold 3 times between req & done.
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-- busy has to hold each cycle between req & done.
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-- This assertion holds
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SERE_0_a : assert always {req} |=> {{valid[->3]} && {(busy and not done)[+]}; not busy and done};
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 10);
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-- synthesis translate_on
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end architecture psl;
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