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43 lines
746 B
43 lines
746 B
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity yosys_anyconst is
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port (
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clk : in std_logic
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);
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end entity yosys_anyconst;
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architecture psl of yosys_anyconst is
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attribute anyconst : boolean;
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signal a: std_logic;
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signal b: natural;
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attribute anyconst of a : signal is true;
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attribute anyconst of b : signal is true;
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begin
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- a should always be high
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ANY_ASSUME_0_a : assume always a;
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-- This assertion holds
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ANY_ASSERT_0_a : assert always a;
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-- a should always be high
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ANY_ASSUME_1_a : assume always b = 42;
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-- This assertion holds
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ANY_ASSERT_1_a : assert always b = 42;
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end architecture psl;
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