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96 lines
2.2 KiB
96 lines
2.2 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use std.env.all;
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package pkg is
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component sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic
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);
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end component sequencer;
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component hex_sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic_vector(3 downto 0)
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);
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end component hex_sequencer;
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function to_bit (a : in character) return std_logic;
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function to_hex (a : in character) return std_logic_vector;
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-- synthesis translate_off
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procedure stop_sim (signal clk : in std_logic; cycles : in natural; add_cycles : in natural := 2);
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-- synthesis translate_on
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end package pkg;
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package body pkg is
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function to_bit (a : in character) return std_logic is
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variable ret : std_logic;
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begin
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case a is
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when '0' | '_' => ret := '0';
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when '1' | '-' => ret := '1';
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when others => ret := 'X';
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end case;
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return ret;
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end function to_bit;
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function to_hex (a : in character) return std_logic_vector is
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variable ret : std_logic_vector(3 downto 0);
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begin
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case a is
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when '0' | '_' => ret := x"0";
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when '1' => ret := x"1";
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when '2' => ret := x"2";
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when '3' => ret := x"3";
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when '4' => ret := x"4";
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when '5' => ret := x"5";
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when '6' => ret := x"6";
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when '7' => ret := x"7";
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when '8' => ret := x"8";
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when '9' => ret := x"9";
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when 'a' | 'A' => ret := x"A";
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when 'b' | 'B' => ret := x"B";
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when 'c' | 'C' => ret := x"C";
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when 'd' | 'D' => ret := x"D";
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when 'e' | 'E' => ret := x"E";
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when 'f' | 'F' | '-' => ret := x"F";
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when others => ret := x"X";
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end case;
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return ret;
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end function to_hex;
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-- synthesis translate_off
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procedure stop_sim (signal clk : in std_logic; cycles : in natural; add_cycles : in natural := 2) is
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variable index : natural := cycles + add_cycles;
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begin
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loop
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wait until rising_edge(clk);
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index := index - 1;
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if index = 0 then
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exit;
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end if;
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end loop;
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finish(0);
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end procedure stop_sim;
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-- synthesis translate_on
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end package body pkg;
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