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61 lines
1.7 KiB
61 lines
1.7 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_property is
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port (
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clk : in std_logic
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);
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end entity psl_property;
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architecture psl of psl_property is
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signal req, avalid, busy, adone, data, ddone : std_logic;
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begin
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-- 01234567890123
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SEQ_REQ : sequencer generic map ("_-____________") port map (clk, req);
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SEQ_AVALID : sequencer generic map ("__-___________") port map (clk, avalid);
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SEQ_BUSY : sequencer generic map ("___-_--_______") port map (clk, busy);
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SEQ_ADONE : sequencer generic map ("_______-______") port map (clk, adone);
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SEQ_DATA : sequencer generic map ("________---___") port map (clk, data);
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SEQ_DDONE : sequencer generic map ("___________-__") port map (clk, ddone);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Transfer property
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property transfer_3 is always (
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{req} |=> {{avalid; busy[->3]; adone}; {data[->3]; ddone}}
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);
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-- SERE concatenation operator
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-- RHS starts at one cycle cycle that the LHS ends
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-- This assertion holds
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PROP_0_a : assert transfer_3;
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-- Properties can have parameters
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-- This assertion holds
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property transfer_3_p (boolean v, ad, dd) is always (
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{req} |=> {{v; busy[->3]; ad}; {data[->3]; dd}}
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);
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-- SERE concatenation operator
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-- RHS starts at one cycle cycle that the LHS ends
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-- This assertion holds
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PROP_1_a : assert transfer_3_p(avalid, adone, ddone);
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 13);
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-- synthesis translate_on
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end architecture psl;
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