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175 lines
3.9 KiB
175 lines
3.9 KiB
library ieee;
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use ieee.std_logic_1164.all;
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entity sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic
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);
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end entity sequencer;
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architecture rtl of sequencer is
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signal index : natural := seq'low;
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function to_bit (a : in character) return std_logic is
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variable ret : std_logic;
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begin
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case a is
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when '0' | '_' => ret := '0';
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when '1' | '-' => ret := '1';
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when others => ret := 'X';
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end case;
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return ret;
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end function to_bit;
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if (index < seq'high) then
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index <= index + 1;
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end if;
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end if;
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end process;
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data <= to_bit(seq(index));
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end architecture rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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entity hex_sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic_vector(3 downto 0)
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);
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end entity hex_sequencer;
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architecture rtl of hex_sequencer is
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signal index : natural := seq'low;
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function to_hex (a : in character) return std_logic_vector is
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variable ret : std_logic_vector(3 downto 0);
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begin
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case a is
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when '0' | '_' => ret := x"0";
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when '1' => ret := x"1";
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when '2' => ret := x"2";
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when '3' => ret := x"3";
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when '4' => ret := x"4";
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when '5' => ret := x"5";
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when '6' => ret := x"6";
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when '7' => ret := x"7";
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when '8' => ret := x"8";
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when '9' => ret := x"9";
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when 'a' | 'A' => ret := x"A";
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when 'b' | 'B' => ret := x"B";
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when 'c' | 'C' => ret := x"C";
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when 'd' | 'D' => ret := x"D";
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when 'e' | 'E' => ret := x"E";
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when 'f' | 'F' | '-' => ret := x"F";
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when others => ret := x"X";
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end case;
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return ret;
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end function to_hex;
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if (index < seq'high) then
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index <= index + 1;
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end if;
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end if;
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end process;
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data <= to_hex(seq(index));
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end architecture rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity issue is
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port (
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clk : in std_logic
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);
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end entity issue;
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architecture psl of issue is
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component sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic
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);
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end component sequencer;
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component hex_sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic_vector(3 downto 0)
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);
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end component hex_sequencer;
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signal req, ack : std_logic;
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signal din, dout : std_logic_vector(3 downto 0);
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begin
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-- 0123456789
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SEQ_REQ : sequencer generic map ("_-______-____") port map (clk, req);
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SEQ_DIN : hex_sequencer generic map ("4433344774444") port map (clk, din);
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SEQ_ACK : sequencer generic map ("___-______-__") port map (clk, ack);
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SEQ_DOUT : hex_sequencer generic map ("2244333447744") port map (clk, dout);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Check for two possible values of din/dout
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NEXT_EVENT_0_a : assert always ((req and din = x"4") -> next_event(ack)(dout = x"4"));
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NEXT_EVENT_1_a : assert always ((req and din = x"7") -> next_event(ack)(dout = x"7"));
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-- Check for all possible values of din/dout
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check_transfer : for i in 0 to 15 generate
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signal i_slv : std_logic_vector(din'range);
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begin
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i_slv <= std_logic_vector(to_unsigned(i, 4));
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-- Without name it works
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assert always ((req and din = i_slv) -> next_event(ack)(dout = i_slv));
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-- This errors because of similar names of all asserts
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-- ERROR: Assert `count_id(cell->name) == 0' failed in kernel/rtlil.cc:1613.
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NEXT_EVENT_a : assert always ((req and din = i_slv) -> next_event(ack)(dout = i_slv));
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end generate check_transfer;
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end architecture psl;
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