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67 lines
2.3 KiB
67 lines
2.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere_non_consecutive_repeat_repetition is
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port (
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clk : in std_logic
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);
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end entity psl_sere_non_consecutive_repeat_repetition;
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architecture psl of psl_sere_non_consecutive_repeat_repetition is
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signal req, busy, done : std_logic;
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begin
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-- 0123456789
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SEQ_REQ : sequencer generic map ("_-________") port map (clk, req);
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SEQ_BUSY : sequencer generic map ("__-_-_-___") port map (clk, busy);
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SEQ_DONE : sequencer generic map ("________-_") port map (clk, done);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Non consecutive repetition of 3 cycles with possible padding
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-- busy has to hold on 3 cycles between req & done
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-- This assertion holds
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SERE_0_a : assert always {req} |=> {busy[=3]; done};
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-- Non consecutive repetition of 2 to 4 cycles with possible padding
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-- busy has to hold on 2 to 4 cycles between req & done
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-- This assertion holds
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SERE_1_a : assert always {req} |=> {busy[=2 to 4]; done};
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-- Non consecutive repetition of 5 cycles with possible padding
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-- busy has to hold on 5 cycles between req & done
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-- This assertion holds -> possible PITFALL!
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-- RHS is underspecified, nothing prevents done to hold between or together
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-- with holding busy. For intentioned behaviour, the behaviour of done
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-- has to be described more specificly (see SERE_3_a)
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SERE_2_a : assert always {req} |=> {busy[=5]; done};
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-- Non consecutive repetition of 3 cycles with possible padding
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-- busy has to hold on exactly 3 cycles between req & and the first done
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-- This is a more exact version of the assertions before using
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-- the length-matching and SERE operator &&
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-- This assertion holds
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SERE_3_a : assert always {req} |=> {{{busy[=3]} && {not done[+]}}; done};
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-- Non consecutive repetition of 4 cycles with possible padding
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-- busy has to hold on exactly 4 cycles between req & and the first done
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-- This assertion doesn't hold at cycle 8
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SERE_4_a : assert always {req} |=> {{{busy[=4]} && {not done[+]}}; done};
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 10);
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-- synthesis translate_on
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end architecture psl;
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