Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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T. Meissner 0d5101ee50 Add example for SERE fusion (:) operator 5 years ago
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Makefile Stop simulation after a given number of cycles instead of time 5 years ago
template.vhd Stop simulation after a given number of cycles instead of time 5 years ago
tests.mk Add example for SERE fusion (:) operator 5 years ago