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63 lines
1.4 KiB
63 lines
1.4 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_prev is
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port (
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clk : in std_logic
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);
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end entity psl_prev;
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architecture psl of psl_prev is
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signal valid : std_logic;
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signal a : std_logic;
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signal d : std_logic_vector(3 downto 0);
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begin
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-- 0123456789012
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SEQ_VALID : sequencer generic map ("_-_-_-_-_-_-_") port map (clk, valid);
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SEQ_A : sequencer generic map ("__--__--__--_") port map (clk, a);
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SEQ_D : hex_sequencer generic map ("0011223344556") port map (clk, d);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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PREV_0_a : assert always (valid -> a = prev(a));
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-- This assertion should hold
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-- prev() with vector parameter isn't supported yet
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-- Workaround: VHDL glue logic
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-- PREV_1_a : assert always (valid -> d = prev(d));
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-- Workaround with VHDL glue logic generating the
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-- previous value of d
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d_reg : block is
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signal d_prev : std_logic_vector(3 downto 0);
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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d_prev <= d;
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end if;
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end process;
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PREV_2_a : assert always (valid -> d = d_prev);
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end block d_reg;
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 13);
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-- synthesis translate_on
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end architecture psl;
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