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37 lines
526 B
37 lines
526 B
vunit issue_vunit (issue(psl)) {
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- GHDL crash if condition evaluates to true
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test_g : if true generate
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-- This assertion holds
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CHECK_0_a : assert always (a -> b);
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end generate test_g;
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}
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library ieee;
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use ieee.std_logic_1164.all;
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entity issue is
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port (
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clk : in std_logic
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);
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end entity issue;
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architecture psl of issue is
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signal a, b : std_logic := '1';
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begin
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a <= '1';
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b <= a;
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end architecture psl;
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