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129 lines
2.6 KiB
129 lines
2.6 KiB
library ieee;
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use ieee.std_logic_1164.all;
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entity hex_sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic_vector(3 downto 0)
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);
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end entity hex_sequencer;
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architecture rtl of hex_sequencer is
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signal index : natural := seq'low;
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function to_hex (a : in character) return std_logic_vector is
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variable ret : std_logic_vector(3 downto 0);
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begin
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case a is
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when '0' | '_' => ret := x"0";
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when '1' => ret := x"1";
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when '2' => ret := x"2";
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when '3' => ret := x"3";
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when '4' => ret := x"4";
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when '5' => ret := x"5";
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when '6' => ret := x"6";
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when '7' => ret := x"7";
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when '8' => ret := x"8";
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when '9' => ret := x"9";
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when 'a' | 'A' => ret := x"A";
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when 'b' | 'B' => ret := x"B";
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when 'c' | 'C' => ret := x"C";
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when 'd' | 'D' => ret := x"D";
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when 'e' | 'E' => ret := x"E";
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when 'f' | 'F' | '-' => ret := x"F";
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when others => ret := x"X";
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end case;
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return ret;
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end function to_hex;
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if (index < seq'high) then
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index <= index + 1;
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end if;
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end if;
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end process;
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data <= to_hex(seq(index));
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end architecture rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity issue is
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port (
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clk : in std_logic
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);
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end entity issue;
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architecture psl of issue is
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signal a : std_logic_vector(3 downto 0);
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begin
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SEQ_C : entity work.hex_sequencer generic map ("0123456789ABCDEF") port map (clk, a);
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end architecture psl;
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library ieee;
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use ieee.std_logic_1164.all;
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use std.env.all;
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entity test_issue is
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end entity test_issue;
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architecture sim of test_issue is
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signal clk : std_logic := '1';
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begin
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clk <= not clk after 500 ps;
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DUT : entity work.issue(psl) port map (clk);
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-- stop simulation after 30 cycles
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process
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variable index : natural := 29;
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begin
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loop
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wait until rising_edge(clk);
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index := index - 1;
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exit when index = 0;
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end loop;
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stop(0);
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end process;
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end architecture sim;
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vunit issue_1850_vu (issue(psl)) {
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- A simple check for counter increasing
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-- Nested generate leads to a crash
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test : if true generate
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counter_check : for i in 0 to 14 generate
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SERE_4_a : assert always
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{a = std_logic_vector(to_unsigned(i, 4))}
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|=>
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{a = std_logic_vector(to_unsigned(i + 1, 4))};
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end generate counter_check;
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end generate test;
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}
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