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34 lines
531 B
34 lines
531 B
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_always is
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port (
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clk : in std_logic
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);
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end entity psl_always;
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architecture psl of psl_always is
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signal a : std_logic;
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begin
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SEQ : sequencer generic map ("_-_-_") port map (clk, a);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Signal a has to be low at cycle 0 only
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WITHOUT_ALWAYS_a : assert a;
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-- Signal a has to be low forever
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WITH_ALWAYS_a : assert always a;
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end architecture psl;
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