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40 lines
604 B
40 lines
604 B
library ieee;
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use ieee.std_logic_1164.all;
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entity sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic
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);
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end entity sequencer;
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architecture rtl of sequencer is
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signal cycle : natural := 0;
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signal ch : character;
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if (cycle < seq'length) then
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cycle <= cycle + 1;
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end if;
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end if;
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end process;
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ch <= seq(cycle+1);
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data <= '0' when ch = '0' or ch = '_' else
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'1' when ch = '1' or ch = '-' else
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'X';
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end architecture rtl;
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