Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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[tasks]
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sere_0 bmc
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sere_1 bmc
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sere_2 bmc
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sere_3 bmc
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all bmc
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bmc all
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[options]
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depth 25
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bmc: mode bmc
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[engines]
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bmc: smtbmc z3
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[script]
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sere_0: ghdl --std=08 -gformal=SERE_0 pkg.vhd sequencer.vhd psl_vunit.vhd psl_vunit.psl -e psl_vunit
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sere_1: ghdl --std=08 -gformal=SERE_1 pkg.vhd sequencer.vhd psl_vunit.vhd psl_vunit.psl -e psl_vunit
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sere_2: ghdl --std=08 -gformal=SERE_2 pkg.vhd sequencer.vhd psl_vunit.vhd psl_vunit.psl -e psl_vunit
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sere_3: ghdl --std=08 -gformal=SERE_3 pkg.vhd sequencer.vhd psl_vunit.vhd psl_vunit.psl -e psl_vunit
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all: ghdl --std=08 -gformal=ALL pkg.vhd sequencer.vhd psl_vunit.vhd psl_vunit.psl -e psl_vunit
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prep -top psl_vunit
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[files]
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../src/pkg.vhd
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../src/sequencer.vhd
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../src/psl_vunit.vhd
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../src/psl_vunit.psl
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